1. Field of Invention
The present invention relates to a method of fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a non-volatile memory.
2. Description of Related Art
The non-volatile memory allows multiple and repetitive writing, reading and erasure operations, and the storage data are retained even after the power supply is discontinued. Except for the aforementioned advantages, the non-volatile memory also has other advantages, including rapid writing/erasure rate, large storage capacity and compactness, and has been widely applied in the electronic products and personal computers.
In general, the non-volatile memory cell is comprised of a stacked gate, made or doped polysilicon and consisting of a floating gate and a control gate. A dielectric layer is disposed between the floating gate and the control gate, while a tunnel oxide layer is located between the floating gate and the substrate. The floating gate is disposed between the substrate and the control and in a “floated” state (i.e. not being electrically connected with any circuit). The control gate is electrically connected with the word line.
For the memory device, if the gate couple ratio (GCR) between the floating gate and the control gate is larger, the required operation voltage can be lower and the efficiency of the device can be increased. In order to increase the gate couple ratio, either the capacitance of the inter-gate dielectric layer is increased or the capacitance of the tunnel oxide layer is decreased. For increasing the capacitance of the inter-gate dielectric layer, it is necessary to increase the overlapped area between the control gate and the floating gate.
FIG. 1 is a cross-sectional view of a prior non-volatile memory structure. The memory structure includes a substrate 100, a tunnel oxide layer 102 floating gates 104, a inter-gate dielectric layer 106, a conductive layer 108, source/drain regions 110 and a oxide layer 112. The floating gate 104 consists or two different conductive layers 104a and 104b. After patterning the conductive layer 104a of the floating gates 104, in order to increase the GCR, another conductive layer 104b is defined and patterned by photolithography and etching. Due to many uncontrollable factors of photolithography, misalignment often occurs to the floating gates during the photolithography process. Especially if misalignment happens during the photolithography and etching process of the conductive layer 104b, bridging between the separate floating gates may occur and the following deposition of the inter-gate dielectric layer 106 becomes uneven, leading to varying GCR of the floating gates.